Many input terminals of a MOS integrated circuit are connected to the gate electrodes of respective input MOS field-effect transistors and many output terminals of the integrated circuit are connected to the drain regions of respective output MOS field-effect transistors.
It is known that the terminals of an integrated circuit are subject to accidental contacts with electrically-charged bodies, both during their manufacture and during assembly in a circuit unit or in operation, so that potential differences, possibly of very considerable magnitude, may be created between the gate electrodes of the input transistors, or the drain regions of the output transistors, and the substrate of semiconductor material on which the integrated circuit is formed. In the first case, as soon as the potential difference exceeds the dielectric strength threshold of the gate insulation, the transistor is destroyed by the electrostatic discharge, which develops through the insulation and, in the second case, a similar destructive effect occurs as soon as the potential difference exceeds the reverse breakdown threshold of the drain junction. By way of example, in a CMOS integrated circuit manufactured with 1.2 .mu.m technology (that is, with minimum gate dimensions of 1.2 .mu.m), the destructive-breakdown potential is 12-14 V for the input transistors and about 12 V for the output transistors.
Various devices are known for protecting the input and output terminals from electrostatic discharges. Some of these use resistors in series and diodes which are in series and/or in parallel and are integrated in the substrate on which the integrated circuit is formed, in order to limit or shunt the currents due to the electrostatic discharges, and are suitable essentially for protecting input terminals; others use thyristor or SCR (silicon-controlled rectifier) structures in parallel and may be used for protecting both input and output terminals. An SCR structure is very advantageous since it has a very low resistance when it is conducting and is very efficient in energy terms since the heat produced during conduction is distributed in a relatively large volume. However, in many applications, the striking potential of the SCR is much higher than the destructive-breakdown potential of the input and output transistors. Modified SCR structures which provide measures for lowering the striking potential are therefore used.
For example, in a known device described in the article published on pages 21 and 22 of IEEE Electron Device Letters, Vol. 12, No. 1, January 1991, a MOS transistor biased for cut-off is associated with a lateral SCR and causes striking of the SCR by means of the charge generated by the reverse conduction through its drain junction. The striking potential value can be adjusted to a certain extent by modification of the geometry of the gate electrode, advantage being taken of the fact that the reverse conduction voltage decreases with the length of the gate.
This known structure functions satisfactorily only if the anode and cathode regions of the SCR are quite far apart and/or if adequate insulation is provided between these regions to prevent the formation of a parasitic P-channel MOS transistor, biased for conduction, in parallel with the SCR and having a conduction threshold below the striking threshold of the protection device. This involves the use of a relatively large area of the substrate.